A new method is proposed to distribute the steady-state output voltage errors in a two-output forward converter. The cross-regulation among the two output voltages aredescribed in terms of the circuit parameters. An objective function is formed for each of the two outputs to track its reference within the specified error. The weighting feedback gains of the two output voltages can be determined by the presented control scheme which optimizes the objective function. The proposed method is suitable for a two-output system without a dominant load

The paper proposes a high linear CMOS continuous-time common-mode feedback circuit. Theoretical analysis and SPICE simulation results are provided. Two circuit applications of the proposed configuration, one is the fully differential folded-cascode op-amp, the other is the Multiply-by-Two circuit which is the key component in the popular 1.5bit/stage pipelined ADC are designed. The Comparison results show that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits

We discuss three different models for the simulation of integer-N CP-PLLs, namely the continuous time and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of approximated models are analyzed in terms of settling time and output spectral purity estimation for fast settling PLLs up to fourth order. As a case study the three models are applied to a fast switching PLL targeting WiMedia MB-OFDM UWB systems