This paper analyzes the impact of parasitic capacitances in the performance of split capacitive-based digital-to-analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the main responsible for the nonlinear behavior of these arrays, particularly for low-to-medium resolution converters. In order to validate the analysis, two versions of a complete low-power, low-voltage successive-approximation register analog-to-digital converter (ADC), intended for a disposable multi-channel bio-medical monitoring system, have been fabricated in a 0.35µm standard complementary metal-oxide-semiconductor technology. The only difference between these two prototypes is that in one of them, the capacitive array is surrounded by dummy capacitors, while in the other prototype is not. Hence, the former achieves better mismatch performance at the expense of increased parasitics. The experimental results demonstrate that the version without dummy capacitors obtains higher effective resolution than the ADC with dummies, the power consumption being essentially the same for both prototypes, namely: 130nW at 2kS/s from a 1-V supply. These results are in full agreement with the analysis reported in the paper and confirm the proposed sizing procedure.