We present a two-integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130?nm CMOS technology is continuously tuneable from 3.1 to 10.6?GHz. The circuit die area is less than 0.013?mm2, leading to a figure-of-merit FOMA of ?176.7?dBc/Hz at the upper frequency. The supply voltage is 1.2?V, and the power consumption is 7?mW at the lower frequency and 13?mW at the upper frequency.

The design of a novel single-clock-cycle 64-bit binary comparator is here proposed. It is based on a new parallel-prefix structure that allows an energy-delay-product ?26% lower than previous proposals to be reached, when implemented with the ST 90-nm 1-V CMOS process. The main innovation is that the switching activity of the internal signals of the circuit is significantly reduced.

A new design approach to maximize the bandwidth of three-stage operational amplifiers is presented. The proposed approach allows the amplifier bandwidth to be significantly enhanced with respect to that resulting from using existing design strategies. Design examples in a commercial 0.35-µm CMOS technology prove the effectiveness of the proposed criterion.